Management of parasitic bipolars in modular high power LDMOS technology
The result's identifiers
Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F26821532%3A_____%2F16%3AN0000008" target="_blank" >RIV/26821532:_____/16:N0000008 - isvavai.cz</a>
Result on the web
<a href="http://ieeexplore.ieee.org/document/7599646/" target="_blank" >http://ieeexplore.ieee.org/document/7599646/</a>
DOI - Digital Object Identifier
<a href="http://dx.doi.org/10.1109/ESSDERC.2016.7599646" target="_blank" >10.1109/ESSDERC.2016.7599646</a>
Alternative languages
Result language
angličtina
Original language name
Management of parasitic bipolars in modular high power LDMOS technology
Original language description
M. Agam, J. Pjenčák, D. Prejda, A. Suwhanov, T. Yao and L. Šeliga, Management of parasitic bipolars in modular high power LDMOS technology, 46th European Solid-State Device Research Conference (ESSDERC), Lausanne, 2016, pp. 303-306. doi: 10.1109/ESSDERC.2016.7599646: Integration of isolated LDMOS transistors in smart power process is subjected to bipolar parasitics due to multi layers constructions that are needed for high voltage operation. These parasitics need to be minimized to assure proper circuit functionality. Several approaches for parasitics reduction are suggested: DTI (Deep Trench Isolation) module optimization, NLDMOS and PLDMOS device construction considerations, and lateral and vertical isolation techniques. Creating circuit level parasitic model which can be turned on and off is essential to verify circuit functionality of the improved isolation.
Czech name
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Czech description
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Classification
Type
D - Article in proceedings
CEP classification
JA - Electronics and optoelectronics
OECD FORD branch
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Result continuities
Project
<a href="/en/project/TH01010419" target="_blank" >TH01010419: Development of Novel Technologies for Trench Insulated Gate Bipolar Transistors (TIGBT) Manufacturing</a><br>
Continuities
P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)
Others
Publication year
2016
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů
Data specific for result type
Article name in the collection
2016 46th European Solid-State Device Research Conference (ESSDERC)
ISBN
978-1-5090-2969-3
ISSN
2378-6558
e-ISSN
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Number of pages
4
Pages from-to
303-306
Publisher name
IEEE
Place of publication
Lausanne, Switzerland
Event location
Lausanne, Switzerland
Event date
Sep 12, 2016
Type of event by nationality
WRD - Celosvětová akce
UT code for WoS article
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