On performance estimation of a scalable VLIW soft-core in XILINX FPGAs
The result's identifiers
Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F46747885%3A24220%2F13%3A%230002862" target="_blank" >RIV/46747885:24220/13:#0002862 - isvavai.cz</a>
Result on the web
<a href="http://www.scopus.com/record/display.url?origin=AuthorProfile&view=basic&eid=2-s2.0-84881354575" target="_blank" >http://www.scopus.com/record/display.url?origin=AuthorProfile&view=basic&eid=2-s2.0-84881354575</a>
DOI - Digital Object Identifier
<a href="http://dx.doi.org/10.1109/DDECS.2013.6549813" target="_blank" >10.1109/DDECS.2013.6549813</a>
Alternative languages
Result language
angličtina
Original language name
On performance estimation of a scalable VLIW soft-core in XILINX FPGAs
Original language description
This paper presents performance estimations for a scalable VLIW soft-core in various XILINX FPGAs. It covers the low-cost low-power devices as well as the latest high-end FPGA families. The results represent the maximal clock frequency of the complete design including the processor core and the code and data memories. A scaling test has been done as well. In this case, the VLIW soft-core has incorporated various numbers of execution units and issue slots. It shows that the clock rate of the core scalesmuch better with the number of execution units than proposed in estimations for standard-cell-based designs. It does not always create a lower clock rate of the design. Moreover, the highest possible clock rate shows some unexpected behaviour, when scaling the number of execution units. In some cases, a higher number of execution units cause no clock rate penalty. Finally, both ways of scaling the performance are compared with each other and some conclusions for a design space exploratio
Czech name
—
Czech description
—
Classification
Type
D - Article in proceedings
CEP classification
JC - Computer hardware and software
OECD FORD branch
—
Result continuities
Project
<a href="/en/project/LD13019" target="_blank" >LD13019: Improvement in Reliability of Nano-scale circuits</a><br>
Continuities
P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)<br>S - Specificky vyzkum na vysokych skolach
Others
Publication year
2013
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů
Data specific for result type
Article name in the collection
16th International Symposium on Design and Diagnostics of Electronic Circuits and Systems
ISBN
978-1-4673-6135-4
ISSN
—
e-ISSN
—
Number of pages
6
Pages from-to
181-186
Publisher name
IEEE, 345 E 47TH ST, NEW YORK, NY 10017 USA
Place of publication
—
Event location
Karlovy Vary; Czech Republic
Event date
Jan 1, 2013
Type of event by nationality
WRD - Celosvětová akce
UT code for WoS article
000325168900039