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On performance estimation of a scalable VLIW soft-core on Altera and Xilinx FPGA platforms

The result's identifiers

  • Result code in IS VaVaI

    <a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F46747885%3A24220%2F13%3A%230002860" target="_blank" >RIV/46747885:24220/13:#0002860 - isvavai.cz</a>

  • Result on the web

    <a href="http://www.scopus.com/record/display.url?origin=AuthorProfile&view=basic&eid=2-s2.0-84890537348" target="_blank" >http://www.scopus.com/record/display.url?origin=AuthorProfile&view=basic&eid=2-s2.0-84890537348</a>

  • DOI - Digital Object Identifier

Alternative languages

  • Result language

    angličtina

  • Original language name

    On performance estimation of a scalable VLIW soft-core on Altera and Xilinx FPGA platforms

  • Original language description

    This paper presents performance estimations for a scalable VLIW soft-core implemented in various XILINX and ALTERA FPGAs. It covers the low-cost low-power devices as well as the latest high-end FPGA families of both providers. The results present the maximal clock frequency of the complete design including the processor core and the code and data memories. In the soft-core scaling experiment, the number of available execution units is scaled from 1 to 12. In the technology scaling experiment, the core was mapped to devices of semiconductor technology nodes from 90 nm down to the latest 28nm technology. The experiments show some interesting behaviour. For example, for small-sized cores the XILINX board outperforms the ALTERA, while for larger sized cores this situation completely changes. Finally, both FPGA platforms and ways of scaling the performance are compared with each other and some conclusions for a design space exploration of soft-cores are presented.

  • Czech name

  • Czech description

Classification

  • Type

    D - Article in proceedings

  • CEP classification

    JC - Computer hardware and software

  • OECD FORD branch

Result continuities

  • Project

    <a href="/en/project/LD13019" target="_blank" >LD13019: Improvement in Reliability of Nano-scale circuits</a><br>

  • Continuities

    P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)<br>S - Specificky vyzkum na vysokych skolach

Others

  • Publication year

    2013

  • Confidentiality

    S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Data specific for result type

  • Article name in the collection

    18th International Conference on Applied Electronics, AE 2013

  • ISBN

    9788026101666

  • ISSN

    1803-7232

  • e-ISSN

  • Number of pages

    4

  • Pages from-to

    209-212

  • Publisher name

    IEEE Computer Society

  • Place of publication

  • Event location

    Pilsen; Czech Republic

  • Event date

    Jan 1, 2013

  • Type of event by nationality

    WRD - Celosvětová akce

  • UT code for WoS article