A new method for in situ measurement of parameters and degradation processes in modern nanoscale programmable devices

Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F46747885%3A24220%2F14%3A%230003125" target="_blank" >RIV/46747885:24220/14:#0003125 - isvavai.cz</a>
Result on the web
<a href="http://apps.webofknowledge.com/full_record.do?product=UA&search_mode=GeneralSearch&qid=3&SID=T2NB6uw5KFzUlFqSh8f&page=1&doc=1" target="_blank" >http://apps.webofknowledge.com/full_record.do?product=UA&search_mode=GeneralSearch&qid=3&SID=T2NB6uw5KFzUlFqSh8f&page=1&doc=1</a>
DOI - Digital Object Identifier
<a href="http://dx.doi.org/10.1016/j.micpro.2014.04.008" target="_blank" >10.1016/j.micpro.2014.04.008</a>

Result language
angličtina
Original language name
A new method for in situ measurement of parameters and degradation processes in modern nanoscale programmable devices
Original language description
This paper presents a new method and results from measurement of internal parameters of programmable nanoscale circuits, namely Xilinx FPGA devices and especially Zynq SoC devices designed on 28 nm TSMC's technology and older 45 nm Spartan 6 device as well as Xilinx Virtex product lines. The method utilizes a new undersampling approach for frequency measurement and an easy way of processing BRAM data streams. The proposed flexible circuits have been used in various measurements of timing parameters anddelays in FPGAs, including measurements or detection of the aging issues. The paper presents results of measurements under various core voltage values as performed on selected Xilinx FPGA platforms, including key results about limited usability of the latest 28 nm devices under accelerated conditions and possibility of studying or mitigating aging effects in FPGAs. The paper presents rare results of experiments, real measurements and data available from current as well as previous techno
Czech name
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Czech description
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Type
J<sub>x</sub> - Unclassified - Peer-reviewed scientific article (Jimp, Jsc and Jost)
CEP classification
JC - Computer hardware and software
OECD FORD branch
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Project
<a href="/en/project/LD13019" target="_blank" >LD13019: Improvement in Reliability of Nano-scale circuits</a><br>
Continuities
P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)<br>S - Specificky vyzkum na vysokych skolach

Publication year
2014
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

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