Fractional phase-locked loop frequency synthesizer
The result's identifiers
Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F49777513%3A23220%2F03%3A00000025" target="_blank" >RIV/49777513:23220/03:00000025 - isvavai.cz</a>
Result on the web
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DOI - Digital Object Identifier
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Alternative languages
Result language
angličtina
Original language name
Fractional phase-locked loop frequency synthesizer
Original language description
The major difficulties are spurious signals generated in fractional divider system. In this paper, the new fractional PLL frequency synthesizer with sigma-delta modulator is described. A complete fractional PLL was simulated, constructed and measured.
Czech name
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Czech description
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Classification
Type
D - Article in proceedings
CEP classification
JA - Electronics and optoelectronics
OECD FORD branch
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Result continuities
Project
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Continuities
Z - Vyzkumny zamer (s odkazem do CEZ)
Others
Publication year
2003
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů
Data specific for result type
Article name in the collection
SCS 2003
ISBN
0-7803-7979-9
ISSN
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e-ISSN
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Number of pages
4
Pages from-to
129-132
Publisher name
Technical University of Iasi
Place of publication
Iasi
Event location
Iasi
Event date
Jul 9, 2003
Type of event by nationality
EUR - Evropská akce
UT code for WoS article
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