Fractional Frequency Synthesizers Based on Flying Adder Principle Description and Simulations Results

Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F49777513%3A23220%2F11%3A43899143" target="_blank" >RIV/49777513:23220/11:43899143 - isvavai.cz</a>
Result on the web
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DOI - Digital Object Identifier
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Result language
angličtina
Original language name
Fractional Frequency Synthesizers Based on Flying Adder Principle Description and Simulations Results
Original language description
Frequency synthesis is one of the most important and most actively researched subjects in the field of VLSI mixed-signal circuit design. Among the existing techniques in this area, phase locked loop fractional architecture is a widely used one for generating frequencies which are not integer multiple of the input reference frequency. Flying-Adder architecture is an emerging technique which is based on a new concept time-average-frequency, to generate frequencies. This paper presents fractional frequencysynthesizer architecture based on concept flying-adder and phase locked loop principle. The simulation results concerning this system are presented.
Czech name
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Czech description
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Project
<a href="/en/project/EE2.4.12.0107" target="_blank" >EE2.4.12.0107: Parnership in electrotechnics and industries</a><br>
Continuities
P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)

Publication year
2011
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Article name in the collection
RECENT RESEARCHES in CIRCUITS, SYSTEMS and SIGNAL PROCESSING
ISBN
978-1-61804-017-6
ISSN
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e-ISSN
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Number of pages
6
Pages from-to
118-123
Publisher name
WSEAS Press
Place of publication
Athens
Event location
Corfu, Řecko
Event date
Jul 14, 2011
Type of event by nationality
WRD - Celosvětová akce
UT code for WoS article
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