Very high resolution time measurement in FPGA
The result's identifiers
Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F49777513%3A23220%2F14%3A43923472" target="_blank" >RIV/49777513:23220/14:43923472 - isvavai.cz</a>
Result on the web
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DOI - Digital Object Identifier
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Alternative languages
Result language
angličtina
Original language name
Very high resolution time measurement in FPGA
Original language description
The paper describes possibility of time measurement in FPGA with very high resolution. There are described methods to obtain the resolution. Block diagram of the design which is implemented in FPGA are shown. Simulations and measurements are mentioned toprove the resolution.
Czech name
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Czech description
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Classification
Type
D - Article in proceedings
CEP classification
JA - Electronics and optoelectronics
OECD FORD branch
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Result continuities
Project
<a href="/en/project/ED2.1.00%2F03.0094" target="_blank" >ED2.1.00/03.0094: Regional Innovation Centre for Electrical Engineering (RICE)</a><br>
Continuities
P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)<br>S - Specificky vyzkum na vysokych skolach
Others
Publication year
2014
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů
Data specific for result type
Article name in the collection
22nd Telecommunications Forum TELFOR 2014 Proceedings of Papers
ISBN
978-1-4799-6190-0
ISSN
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e-ISSN
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Number of pages
4
Pages from-to
745-748
Publisher name
IEEE
Place of publication
Bělehrad
Event location
Bělehrad, Srbsko
Event date
Nov 25, 2014
Type of event by nationality
WRD - Celosvětová akce
UT code for WoS article
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