Consultations and development in field of design and simulations of CPLD and FPGA devices and design embedded systems

Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F49777513%3A23220%2F19%3A43957314" target="_blank" >RIV/49777513:23220/19:43957314 - isvavai.cz</a>
Alternative codes found
RIV/49777513:23220/20:43961182 RIV/49777513:23220/21:43963892 RIV/49777513:23220/22:43967089
Result on the web
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DOI - Digital Object Identifier
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Result language
angličtina
Original language name
Consultations and development in field of design and simulations of CPLD and FPGA devices and design embedded systems
Original language description
Subject of the research were consultations and development in field of design of CPLD and FPGA devices and embedded systems, which includes following topics: Specification, design and verification of USTER CCU7 FPGA System Controller which includes UART16550A with FIFOs, Intelligent Measurement Head Interface (iMH) Controller, custom specific features and powerup sequencing. Specification, design and verification of COMe bBD7 CPLD System Controller. Development and tests of KCPLD library with new Safe BIOS implementation. Specification and design of LHT EED CPLD System Controller which includes Safe CPLD FW update, Valens FW update interfaces, FPGA FW configuration flash update interface and powerup sequencing. Proposal of specification of new KCPLD library with Flat Register Space layout and new system peripherals.
Czech name
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Czech description
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Publication year
2019
Confidentiality
C - Předmět řešení projektu podléhá obchodnímu tajemství (§ 504 Občanského zákoníku), ale název projektu, cíle projektu a u ukončeného nebo zastaveného projektu zhodnocení výsledku řešení projektu (údaje P03, P04, P15, P19, P29, PN8) dodané do CEP, jsou upraveny tak, aby byly zveřejnitelné.

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