Konzultace a vývoj v oblasti návrhu a simulací obvodů CPLD a FPGA a návrhu embedded systémů
The result's identifiers
Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F49777513%3A23220%2F20%3A43961182" target="_blank" >RIV/49777513:23220/20:43961182 - isvavai.cz</a>
Alternative codes found
RIV/49777513:23220/19:43957314 RIV/49777513:23220/21:43963892 RIV/49777513:23220/22:43967089
Result on the web
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DOI - Digital Object Identifier
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Alternative languages
Result language
čeština
Original language name
Consultations and development in field of design and simulations of CPLD and FPGA devices and design embedded systems
Original language description
Subject of the research were consultations and development in field of design of CPLD and FPGA devices and embedded systems, which includes following topics: Specification, design and verification of Lufthansa EED CPLD System Controller which includes UARTs with FIFOs, FW update, Valens FW update interfaces, FPGA FW configuration flash update interface and powerup sequencing. Specification, design and verification of Lufthansa EED FPGA Video Processing Unit which includes PCIe, HDMI sink, DDR3L, mSGDMA, I2S sink, SPI and I2C. Specification, design and verification of Lufthansa MCU CPLD System Controller which includes UARTs with FIFOs, FW update, Valens FW update interfaces and powerup sequencing. Specification, design and verification of Carried Board COMe A2T7 CPLD System Controller. Specification, design and verification of Module COMe mAL1 CPLD System Controller.
Czech name
Consultations and development in field of design and simulations of CPLD and FPGA devices and design embedded systems
Czech description
Subject of the research were consultations and development in field of design of CPLD and FPGA devices and embedded systems, which includes following topics: Specification, design and verification of Lufthansa EED CPLD System Controller which includes UARTs with FIFOs, FW update, Valens FW update interfaces, FPGA FW configuration flash update interface and powerup sequencing. Specification, design and verification of Lufthansa EED FPGA Video Processing Unit which includes PCIe, HDMI sink, DDR3L, mSGDMA, I2S sink, SPI and I2C. Specification, design and verification of Lufthansa MCU CPLD System Controller which includes UARTs with FIFOs, FW update, Valens FW update interfaces and powerup sequencing. Specification, design and verification of Carried Board COMe A2T7 CPLD System Controller. Specification, design and verification of Module COMe mAL1 CPLD System Controller.
Classification
Type
V<sub>souhrn</sub> - Summary research report
CEP classification
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OECD FORD branch
20206 - Computer hardware and architecture
Result continuities
Project
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Continuities
N - Vyzkumna aktivita podporovana z neverejnych zdroju
Others
Publication year
2020
Confidentiality
C - Předmět řešení projektu podléhá obchodnímu tajemství (§ 504 Občanského zákoníku), ale název projektu, cíle projektu a u ukončeného nebo zastaveného projektu zhodnocení výsledku řešení projektu (údaje P03, P04, P15, P19, P29, PN8) dodané do CEP, jsou upraveny tak, aby byly zveřejnitelné.
Data specific for result type
Number of pages
1
Place of publication
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Publisher/client name
KONTRON ECT design s.r.o.
Version
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