Temperature Profile Optimization for Vacuum Soldering of Components on Heat Sink
The result's identifiers
Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F49777513%3A23220%2F25%3A43976263" target="_blank" >RIV/49777513:23220/25:43976263 - isvavai.cz</a>
Result on the web
<a href="https://ieeexplore.ieee.org/document/11222486" target="_blank" >https://ieeexplore.ieee.org/document/11222486</a>
DOI - Digital Object Identifier
<a href="http://dx.doi.org/10.23919/EMPC63132.2025.11222486" target="_blank" >10.23919/EMPC63132.2025.11222486</a>
Alternative languages
Result language
angličtina
Original language name
Temperature Profile Optimization for Vacuum Soldering of Components on Heat Sink
Original language description
Efficient heat dissipation is critical to the reliability and performance of modern high power density electronic systems. Direct soldering of power components to heat sinks minimizes thermal resistance, but traditional reflow soldering methods often result in the formation of voids in the joints, degrading thermal conductivity. This paper focuses on optimizing the temperature profile and vacuum process when soldering electronic components to heat sinks to minimize the occurrence of these voids. Key parameters such as temperature rise rate, time above liquidus (TAL), peak temperature, and most importantly timing and level of vacuum application are described. Using an experiment with different settings of the TAL parameters and vacuum timing, analysis was performed by X-ray inspection and quantification of the percentage of voids. The results show that the correct timing of vacuum application is a critical factor - the most effective vacuum application is after the solder has completely melted. Premature vacuuming leads to an increase in the number of voids, despite the extended TAL time. By optimizing the temperature profile and timing the vacuum correctly, a significant reduction in the occurrence of voids in the joint has been achieved. The paper presents an experimental approach and provides a instructions for achieving a high quality solder joint with minimal thermal resistance.
Czech name
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Czech description
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Classification
Type
D - Article in proceedings
CEP classification
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OECD FORD branch
20201 - Electrical and electronic engineering
Result continuities
Project
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Continuities
S - Specificky vyzkum na vysokych skolach
Others
Publication year
2025
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů
Data specific for result type
Article name in the collection
2025 25th European Microelectronics and Packaging Conference & Exhibition (EMPC)
ISBN
978-1-73950-051-1
ISSN
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e-ISSN
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Number of pages
5
Pages from-to
1-5
Publisher name
IEEE
Place of publication
Piscataway
Event location
Grenoble, France
Event date
Sep 16, 2025
Type of event by nationality
EUR - Evropská akce
UT code for WoS article
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