A Capacitance Multiplier Based on DBTA
The result's identifiers
Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F60162694%3AG43__%2F17%3A00534642" target="_blank" >RIV/60162694:G43__/17:00534642 - isvavai.cz</a>
Result on the web
<a href="http://ieeexplore.ieee.org/document/8124988/" target="_blank" >http://ieeexplore.ieee.org/document/8124988/</a>
DOI - Digital Object Identifier
<a href="http://dx.doi.org/10.1109/NORCHIP.2017.8124988" target="_blank" >10.1109/NORCHIP.2017.8124988</a>
Alternative languages
Result language
angličtina
Original language name
A Capacitance Multiplier Based on DBTA
Original language description
The Design of integrated circuits uses the Capacitance Multipliers for the realization of large-valued on-chip capacitances. The capacitance multiplier can save the valuable space on the chip in exchange for use one active element and two grounded passive components. The final multiplied capacitance is bigger than one real on-chip capacitance, moreover, the smaller on-chip space is required. The proposed circuit connection uses one active element called DBTA (Differential Input Buffered and Transconductance Amplifier) and two passive grounded component - one resistor and one capacitor whose capacitance is finally multiplied. The transconductance of DBTA or value of the resistor can control the multiplication factor. The active element is composed of current feedback amplifiers for test reasons. The verification of this proposal is ensured by SPICE simulations.
Czech name
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Czech description
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Classification
Type
D - Article in proceedings
CEP classification
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OECD FORD branch
20201 - Electrical and electronic engineering
Result continuities
Project
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Continuities
I - Institucionalni podpora na dlouhodoby koncepcni rozvoj vyzkumne organizace
Others
Publication year
2017
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů
Data specific for result type
Article name in the collection
2017 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC)
ISBN
978-1-5386-2844-7
ISSN
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e-ISSN
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Number of pages
5
Pages from-to
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Publisher name
IEEE
Place of publication
Linköping, Sweden
Event location
Linköping, Sweden
Event date
Oct 23, 2017
Type of event by nationality
WRD - Celosvětová akce
UT code for WoS article
000425049100043