Asynchronous Floating-Point Adders and Communication Protocols: A Survey

Result code in IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F61989100%3A27240%2F20%3A10246176" target="_blank" >RIV/61989100:27240/20:10246176 - isvavai.cz</a>

Result on the web

<a href="https://www.mdpi.com/2079-9292/9/10/1687" target="_blank" >https://www.mdpi.com/2079-9292/9/10/1687</a>

DOI - Digital Object Identifier

<a href="http://dx.doi.org/10.3390/electronics9101687" target="_blank" >10.3390/electronics9101687</a>

Result language

angličtina

Original language name

Asynchronous Floating-Point Adders and Communication Protocols: A Survey

Original language description

Addition is the key operation in digital systems, and floating-point adder (FPA) is frequently used for real number addition because floating-point representation provides a large dynamic range. Most of the existing FPA designs are synchronous and their activities are coordinated by clock signal(s). However, technology scaling has imposed several challenges like clock skew, clock distribution, etc., on synchronous design due to presence of clock signal(s). Asynchronous design is an alternate approach to eliminate these challenges imposed by the clock, as it replaces the global clock with handshaking signals and utilizes a communication protocol to indicate the completion of activities. Bundled data and dual-rail coding are the most common communication protocols used in asynchronous design. All existing asynchronous floating-point adder (AFPA) designs utilize dual-rail coding for completion detection, as it allows the circuit to acknowledge as soon as the computation is done; while bundled data and synchronous designs utilizing single-rail encoding will have to wait for the worst-case delay irrespective of the actual completion time. This paper reviews all the existing AFPA designs and examines the effects of the selected communication protocol on its performance. It also discusses the probable outcome of AFPA designed using protocols other than dual-rail coding.

Czech name

—

Czech description

—

Type

J_imp - Article in a specialist periodical, which is included in the Web of Science database

CEP classification

—

OECD FORD branch

20202 - Communication engineering and systems

Project

<a href="/en/project/EF16_019%2F0000867" target="_blank" >EF16_019/0000867: Research Centre of Advanced Mechatronic Systems</a><br>

Continuities

P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)

Publication year

2020

Confidentiality

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Name of the periodical

Electronics

ISSN

2079-9292

e-ISSN

—

Volume of the periodical

9

Issue of the periodical within the volume

10

Country of publishing house

CH - SWITZERLAND

Number of pages

23

Pages from-to

—

UT code for WoS article

000585116800001

EID of the result in the Scopus database

—