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Dual-Rail Asynchronous Logic Multi-Level Implementation

The result's identifiers

  • Result code in IS VaVaI

    <a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F68407700%3A21240%2F14%3A00207600" target="_blank" >RIV/68407700:21240/14:00207600 - isvavai.cz</a>

  • Result on the web

    <a href="http://dx.doi.org/10.1016/j.vlsi.2013.02.002" target="_blank" >http://dx.doi.org/10.1016/j.vlsi.2013.02.002</a>

  • DOI - Digital Object Identifier

    <a href="http://dx.doi.org/10.1016/j.vlsi.2013.02.002" target="_blank" >10.1016/j.vlsi.2013.02.002</a>

Alternative languages

  • Result language

    angličtina

  • Original language name

    Dual-Rail Asynchronous Logic Multi-Level Implementation

  • Original language description

    A synthesis flow oriented on producing the delay-insensitive dual-rail asynchronous logic is proposed. Within this flow, the existing synchronous logic synthesis tools are exploited to design technology independent single-rail synchronous Boolean networkof complex (AND-OR) nodes. Next, the transformation into a dual-rail Boolean network is done. Each node is minimized under the formulated constraint to ensure hazard-free implementation. Then the technology dependent mapping procedure is applied. The MCNC and ISCAS benchmark sets are processed and the area overhead with respect to the synchronous implementation is evaluated. The implementations of the asynchronous logic obtained using the proposed (with AND-OR nodes) and the state-of-the-art (nodes aredesigned based on DIMS, direct logic, NCL) network structures are compared. A method, where nodes are designed as simple (NAND, NOR, etc.) gates is chosen for a detailed comparison. In our approach, the number of completion detection log

  • Czech name

  • Czech description

Classification

  • Type

    J<sub>x</sub> - Unclassified - Peer-reviewed scientific article (Jimp, Jsc and Jost)

  • CEP classification

    JC - Computer hardware and software

  • OECD FORD branch

Result continuities

  • Project

  • Continuities

    I - Institucionalni podpora na dlouhodoby koncepcni rozvoj vyzkumne organizace

Others

  • Publication year

    2014

  • Confidentiality

    S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Data specific for result type

  • Name of the periodical

    Integration, the VLSI Journal

  • ISSN

    0167-9260

  • e-ISSN

  • Volume of the periodical

    47

  • Issue of the periodical within the volume

    1

  • Country of publishing house

    NL - THE KINGDOM OF THE NETHERLANDS

  • Number of pages

    12

  • Pages from-to

    148-159

  • UT code for WoS article

    000328431900016

  • EID of the result in the Scopus database