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Asynchronous Two-Level Logic of Reduced Cost

The result's identifiers

  • Result code in IS VaVaI

    <a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F68407700%3A21230%2F09%3A03154925" target="_blank" >RIV/68407700:21230/09:03154925 - isvavai.cz</a>

  • Result on the web

  • DOI - Digital Object Identifier

Alternative languages

  • Result language

    angličtina

  • Original language name

    Asynchronous Two-Level Logic of Reduced Cost

  • Original language description

    We propose a novel synthesis method of a dual rail asynchronous two-level logic of reduced cost. It is based on a model that operates under so called modified weak constraints. The logic is implemented as a minimized AND-OR structure, together with the completion detection logic. We formulated and proved the product term minimization constraint that ensures a correct logic behavior. We processed the MCNC benchmarks and generated asynchronous two-level logic. The implementation complexity was compared with the state-of-the-art approach. Using our approach, we achieved a significant improvement.

  • Czech name

    Asynchronous Two-Level Logic of Reduced Cost

  • Czech description

    We propose a novel synthesis method of a dual rail asynchronous two-level logic of reduced cost. It is based on a model that operates under so called modified weak constraints. The logic is implemented as a minimized AND-OR structure, together with the completion detection logic. We formulated and proved the product term minimization constraint that ensures a correct logic behavior. We processed the MCNC benchmarks and generated asynchronous two-level logic. The implementation complexity was compared with the state-of-the-art approach. Using our approach, we achieved a significant improvement.

Classification

  • Type

    D - Article in proceedings

  • CEP classification

    JC - Computer hardware and software

  • OECD FORD branch

Result continuities

  • Project

  • Continuities

    Z - Vyzkumny zamer (s odkazem do CEZ)

Others

  • Publication year

    2009

  • Confidentiality

    S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Data specific for result type

  • Article name in the collection

    Proc. of 12th IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop 2009 (DDECS'09)

  • ISBN

    978-1-4244-3339-1

  • ISSN

  • e-ISSN

  • Number of pages

    6

  • Pages from-to

  • Publisher name

    IEEE Computer Society Press

  • Place of publication

    Los Alamitos

  • Event location

    Liberec

  • Event date

    Apr 15, 2009

  • Type of event by nationality

    EUR - Evropská akce

  • UT code for WoS article