Multi-Level Implementation of Asynchronous Logic Using Two-Level Nodes

Result code in IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F68407700%3A21240%2F09%3A00158715" target="_blank" >RIV/68407700:21240/09:00158715 - isvavai.cz</a>

Result on the web

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DOI - Digital Object Identifier

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Result language

angličtina

Original language name

Multi-Level Implementation of Asynchronous Logic Using Two-Level Nodes

Original language description

We propose a novel synthesis method of a dual rail asynchronous two-level logic of reduced cost. It is based on a model that operates under so called modified weak constraints. The logic is implemented as a minimized AND-OR structure, together with the completion detection logic. We formulated and proved the product term minimization constraint that ensures a correct logic behavior. We processed the MCNC benchmarks and generated asynchronous two-level logic. The implementation complexity was compared with the state-of-the-art approach. Using our approach, we achieved a significant improvement.

Czech name

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Czech description

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Type

D - Article in proceedings

CEP classification

JC - Computer hardware and software

OECD FORD branch

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Project

<a href="/en/project/GA102%2F09%2F1668" target="_blank" >GA102/09/1668: SoC circuits reliability and availability improvement</a><br>

Continuities

Z - Vyzkumny zamer (s odkazem do CEZ)

Publication year

2009

Confidentiality

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Article name in the collection

Proc. of 4th Descrete-Event System Design

ISBN

978-3-902661-69-2

ISSN

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e-ISSN

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Number of pages

6

Pages from-to

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Publisher name

University of Valencia

Place of publication

Valencia

Event location

Gandia Beach, Valencia

Event date

Oct 6, 2009

Type of event by nationality

WRD - Celosvětová akce

UT code for WoS article

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