Simulating a Multi-core x86_64 Architecture with Hardware ISA Extension Supporting a Data-Flow Execution Model
The result's identifiers
Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F61989100%3A27740%2F15%3A86093566" target="_blank" >RIV/61989100:27740/15:86093566 - isvavai.cz</a>
Result on the web
<a href="http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=7102471" target="_blank" >http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=7102471</a>
DOI - Digital Object Identifier
<a href="http://dx.doi.org/10.1109/AIMS.2014.41" target="_blank" >10.1109/AIMS.2014.41</a>
Alternative languages
Result language
angličtina
Original language name
Simulating a Multi-core x86_64 Architecture with Hardware ISA Extension Supporting a Data-Flow Execution Model
Original language description
he trend to develop increasingly more intelligent systems leads directly to a considerable demand for more and more computational power. Programming models that aid to exploit the application parallelism with current multi-core systems exist but with limitations. From this perspective, new execution models are arising to surpass limitations to scale up the number of processing elements, while dedicated hardware can help the scheduling of the threads in many-core systems. This paper depicts a data-flow based execution model that exposes to the multi-core x86_64 architecture up to millions of fine-grain threads. We propose to augment the existing architecture with a hardware thread scheduling unit. The functionality of this unit is exposed by means of four dedicated instructions. Results with a pure data-flow application (i.e., Recursive Fibonacci) show that the hardware scheduling unit can load the computing cores (up to 32 in our tests) in a more efficient way than run-time managed threads generated by programming models (e.g., OpenMP and Cilk). Further, our solution shows better scaling and smaller saturation when the number of workers increases.
Czech name
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Czech description
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Classification
Type
D - Article in proceedings
CEP classification
IN - Informatics
OECD FORD branch
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Result continuities
Project
Result was created during the realization of more than one project. More information in the Projects tab.
Continuities
P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)
Others
Publication year
2015
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů
Data specific for result type
Article name in the collection
Proceedings - 2nd International Conference on Artificial Intelligence, Modelling, and Simulation, AIMS 2014
ISBN
978-1-4799-7599-0
ISSN
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e-ISSN
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Number of pages
6
Pages from-to
264-269
Publisher name
Institute of Electrical and Electronics Engineers
Place of publication
New York
Event location
Madrid
Event date
Nov 18, 2014
Type of event by nationality
WRD - Celosvětová akce
UT code for WoS article
000380431100046