Software defined Network-on-Chip for scalable CMPs

Result code in IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F61989100%3A27740%2F16%3A86098616" target="_blank" >RIV/61989100:27740/16:86098616 - isvavai.cz</a>

Result on the web

<a href="http://ieeexplore.ieee.org/document/7568323/" target="_blank" >http://ieeexplore.ieee.org/document/7568323/</a>

DOI - Digital Object Identifier

<a href="http://dx.doi.org/10.1109/HPCSim.2016.7568323" target="_blank" >10.1109/HPCSim.2016.7568323</a>

Result language

angličtina

Original language name

Software defined Network-on-Chip for scalable CMPs

Original language description

Moving from Petascale to Exascale computing necessitates optimizing the micro-architectural to increase the performance/power ratio of multicores (e.g., FLOPS/W). Future manycore processors will contain thousands of low-powered processing elements (kilo-core Chip Multi-Processors - CMPs) to support the execution of a large number of concurrent threads. While data-driven Program eXecution Models (PXMs) are gaining popularity due to the support they provide for thread communication, frequent data exchange among many concurrent threads puts stress on the underlying interconnect subsystem. This results in hotspots and high latency for data packet delivering. As a solution, we propose a scalable Software Defined Network-on-Chip (SDNoC) architecture for future manycore processors. Our design tries to merge the benefits of ring-based NoCs (i.e., performance, energy efficiency) with those brought by dynamic reconfiguration (i.e., adaptation, fault tolerance) while keeping the hard-wired topology (2D-mesh) fixed. To potentially accommodate different application and communication requirements, our interconnect allows mapping different types of topologies (virtual topologies). To allow the software layer to control and monitor the NoC subsystem, few customized instructions supporting a data-driven PXM are added to the core ISA. In experiments, we compared our lightweight reconfigurable architecture to a conventional 2D-mesh interconnection subsystem. Results show that our model allows savings of 39.4% of the chip area and up to 72.4% of the consumed power.

Czech name

—

Czech description

—

Type

D - Article in proceedings

CEP classification

IN - Informatics

OECD FORD branch

—

Project

<a href="/en/project/LQ1602" target="_blank" >LQ1602: IT4Innovations excellence in science</a><br>

Continuities

P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)

Publication year

2016

Confidentiality

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Article name in the collection

2016 INTERNATIONAL CONFERENCE ON HIGH PERFORMANCE COMPUTING &amp; SIMULATION (HPCS 2016)

ISBN

978-1-5090-2088-1

ISSN

—

e-ISSN

—

Number of pages

4

Pages from-to

112-115

Publisher name

IEEE, 345 E 47TH ST, NEW YORK, NY 10017 USA

Place of publication

New York

Event location

Innsbruck

Event date

Jul 18, 2016

Type of event by nationality

EUR - Evropská akce

UT code for WoS article

000389590600015