Hardware Acceleration of Intrusion Detection Systems for High-Speed Networks

Result code in IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F63839172%3A_____%2F18%3A10133026" target="_blank" >RIV/63839172:_____/18:10133026 - isvavai.cz</a>

Result on the web

<a href="https://www.liberouter.org/wp-content/uploads/2018/08/paper.pdf" target="_blank" >https://www.liberouter.org/wp-content/uploads/2018/08/paper.pdf</a>

DOI - Digital Object Identifier

<a href="http://dx.doi.org/10.1145/3230718.3232114" target="_blank" >10.1145/3230718.3232114</a>

Result language

angličtina

Original language name

Hardware Acceleration of Intrusion Detection Systems for High-Speed Networks

Original language description

Intrusion Detection Systems (IDS) are among popular technologies for securing computer networks. However, their high computational complexity makes it hard to meet performance goals of modern high-speed networks. This paper aims at an acceleration of IDS by informed packet discarding. Focusing the limited computational resources available to IDS towards only the most relevant parts of incoming traffic and offloading (bypassing) the rest. We show that this controlled (informed) discarding of well-defined traffic portions helps IDS to achieve better results and compare software and FPGA accelerated discarding implementations.

Czech name

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Czech description

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Type

O - Miscellaneous

CEP classification

—

OECD FORD branch

10201 - Computer sciences, information science, bioinformathics (hardware development to be 2.2, social aspect to be 5.8)

Project

Result was created during the realization of more than one project. More information in the Projects tab.

Continuities

P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)

Publication year

2018

Confidentiality

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů