High-speed stateful packet classifier based on TSS algorithm optimized for off-chip memories
The result's identifiers
Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F63839172%3A_____%2F21%3A10133395" target="_blank" >RIV/63839172:_____/21:10133395 - isvavai.cz</a>
Alternative codes found
RIV/00216305:26230/21:PU139515 RIV/68407700:21240/21:00350413
Result on the web
<a href="http://dx.doi.org/10.1109/DDECS52668.2021.9417060" target="_blank" >http://dx.doi.org/10.1109/DDECS52668.2021.9417060</a>
DOI - Digital Object Identifier
<a href="http://dx.doi.org/10.1109/DDECS52668.2021.9417060" target="_blank" >10.1109/DDECS52668.2021.9417060</a>
Alternative languages
Result language
angličtina
Original language name
High-speed stateful packet classifier based on TSS algorithm optimized for off-chip memories
Original language description
We present a modular out-of-order architecture for stateful packet classification. The architecture uses DDR4 SDRAM memory to store rules and their state information to support millions of rules. The memory access pattern generated by network traffic significantly degrades the performance of the DDR4. Our architecture contains a cache and aggregation queues to negate this effect. Additionally, the memory subsystem supports a read cancellation and uses an out-of-order pipeline to maximize the main memory's effectiveness further. The rule set update is implemented as a non-blocking operation and can be interleaved with lookup operations without any performance decrease, leading to the same execution time for rule update and rule lookup. The architecture is optimized for the modern datacenters network traffic and a small on-chip memory footprint, making it suitable as an accelerator for the Open vSwitch. As a result, our novel architecture configured with 1 million exact match rules can process traffic up to 202 Gbit/s (300 Mp/s) in average case and 51 Gbit/s (76 Mp/s) in the worst case with the use of a common dual-channel 64 bit DDR4-2666 MHz. It uses fewer FPGA resources (excluding cache memory) than the well-known de facto industry standard Xilinx MIG DDR4 controllers. Our proposed architecture enables commodity FPGA cards commonly equipped with DDR4 to process 100 Gbit/s which results in a significant cost reduction of a 100G SmartNICs.
Czech name
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Czech description
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Classification
Type
D - Article in proceedings
CEP classification
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OECD FORD branch
20206 - Computer hardware and architecture
Result continuities
Project
<a href="/en/project/TH04010193" target="_blank" >TH04010193: Acceleration platform for virtual switches</a><br>
Continuities
P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)
Others
Publication year
2021
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů
Data specific for result type
Article name in the collection
Proceedings of 24th International Symposium on Design and Diagnostics of Electronic Circuits and Systems
ISBN
978-1-66543-595-6
ISSN
—
e-ISSN
—
Number of pages
6
Pages from-to
151-156
Publisher name
IEEE
Place of publication
Piscataway , USA
Event location
Vienna, Rakousko
Event date
Apr 7, 2021
Type of event by nationality
WRD - Celosvětová akce
UT code for WoS article
000672620200030