400G Packet Parsing on an FPGA-Based SmartNIC
The result's identifiers
Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F63839172%3A_____%2F23%3A10133581" target="_blank" >RIV/63839172:_____/23:10133581 - isvavai.cz</a>
Result on the web
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DOI - Digital Object Identifier
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Alternative languages
Result language
angličtina
Original language name
400G Packet Parsing on an FPGA-Based SmartNIC
Original language description
CESNET, the NREN (National Research and Education Network) of the Czech Republic, is ready to present its newest research in the area of networking technologies. This includes a 400G SmartNIC, an FPGA-based application built on the NDK (Network Development Kit) framework, and a Linux driver. The NDK is open-source and available on GitHub. It was designed specifically for high-speed packet processing, which is possible due to the MFB and MVB buses that allow the processing of multiple packets in each clock cycle. The proposed demo will showcase packet parsing at 400 Gbps on the Reflex CES XpressSX AGI-FH400G board with an Intel Agilex I-Series FPGA. The whole FPGA design for the demo is built on the NDK, although the Parser unit and the DMA Module6 are not a part of the GitHub repository. The Parser can parse most protocols encapsulated in Ethernet frames, namely VLAN(s), MPLS(s), IPv4, IPv6, ICMP, TCP, UDP, and SCTP. During the demo, packets (stored in a PCAP) will be loaded into the PCAP Player in the FPGA. From there, they will be replayed, going out of the FPGA toward the card's transceiver. The transceiver with a loopback module will return the packets to the FPGA, where the throughput measuring and protocol parsing will occur. The Parser will extract protocol header fields and send them to counters that will be read once the replaying stops. Unparsed packets are also gradually received back into the host PC (via the 400G DMA Module) and stored in a PCAP to be compared with the input PCAP. Ultimately, the throughput will be calculated from the number of transferred bytes in a certain amount of time obtained from the FPGA design.
Czech name
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Czech description
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Classification
Type
O - Miscellaneous
CEP classification
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OECD FORD branch
20206 - Computer hardware and architecture
Result continuities
Project
Result was created during the realization of more than one project. More information in the Projects tab.
Continuities
P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)
Others
Publication year
2023
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů