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Design Methodology of Configurable High Performance Packet Parser for FPGA

The result's identifiers

  • Result code in IS VaVaI

    <a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F63839172%3A_____%2F14%3A10130332" target="_blank" >RIV/63839172:_____/14:10130332 - isvavai.cz</a>

  • Alternative codes found

    RIV/00216305:26230/14:PU111985

  • Result on the web

  • DOI - Digital Object Identifier

Alternative languages

  • Result language

    angličtina

  • Original language name

    Design Methodology of Configurable High Performance Packet Parser for FPGA

  • Original language description

    Packet parsing is among basic operations that are performed at all points of a network infrastructure. Modern networks impose challenging requirements on the performance and configurability of packet parsing modules. However, high-speed parsers often usea significant amount of hardware resources. We propose a novel architecture of a pipelined packet parser for FPGA, which offers low latency in addition to high throughput (over 100 Gb/s). Moreover, the latency, throughput and chip area can be finely tuned to fit the needs of a particular application. The parser is hand-optimized thanks to a direct implementation in VHDL, yet the structure is uniform and easily extensible for new protocols.

  • Czech name

  • Czech description

Classification

  • Type

    D - Article in proceedings

  • CEP classification

    IN - Informatics

  • OECD FORD branch

Result continuities

  • Project

    Result was created during the realization of more than one project. More information in the Projects tab.

  • Continuities

    P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)

Others

  • Publication year

    2014

  • Confidentiality

    S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Data specific for result type

  • Article name in the collection

    2014 IEEE 17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)

  • ISBN

    978-1-4799-4558-0

  • ISSN

    2334-3133

  • e-ISSN

  • Number of pages

    6

  • Pages from-to

    189-194

  • Publisher name

    IEEE Computer Society

  • Place of publication

    Warsaw, Poland

  • Event location

    Warsaw, Poland

  • Event date

    Apr 22, 2014

  • Type of event by nationality

    WRD - Celosvětová akce

  • UT code for WoS article

    000346734200038