Low-Latency Modular Packet Header Parser for FPGA

Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26230%2F12%3APU101888" target="_blank" >RIV/00216305:26230/12:PU101888 - isvavai.cz</a>
Alternative codes found
RIV/63839172:_____/12:00007358
Result on the web
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DOI - Digital Object Identifier
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Result language
angličtina
Original language name
Low-Latency Modular Packet Header Parser for FPGA
Original language description
Packet parsing is the basic operation performed at all points of the network infrastructure. Modern networks impose challenging requirements on the performance and configurability of packet parsing modules, however the high-speed parsers often use very large chip area. We propose novel architecture of pipelined packet parser, which in addition to high throughput (over 100 Gb/s) offers also low latency. Moreover, the latency to throughput ratio can be finely tuned to fit the particular application. The parser is handoptimized thanks to the direct implementation in VHDL, yet the structure is very uniform and easily extensible for new protocols.
Czech name
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Czech description
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Project
Result was created during the realization of more than one project. More information in the Projects tab.
Continuities
P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)<br>Z - Vyzkumny zamer (s odkazem do CEZ)<br>S - Specificky vyzkum na vysokych skolach

Publication year
2012
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Article name in the collection
ACM/IEEE Symposium on Architectures for Networking and Communications Systems
ISBN
978-1-4503-1685-9
ISSN
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e-ISSN
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Number of pages
2
Pages from-to
77-78
Publisher name
Association for Computing Machinery
Place of publication
Austin
Event location
Austin, TX
Event date
Oct 29, 2012
Type of event by nationality
WRD - Celosvětová akce
UT code for WoS article
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