Configurable FPGA Packet Parser for Terabit Networks with Guaranteed Wire-Speed Throughput

Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F63839172%3A_____%2F18%3A10133008" target="_blank" >RIV/63839172:_____/18:10133008 - isvavai.cz</a>
Alternative codes found
RIV/00216305:26230/18:PU127443
Result on the web
<a href="http://dx.doi.org/10.1145/3174243.3174250" target="_blank" >http://dx.doi.org/10.1145/3174243.3174250</a>
DOI - Digital Object Identifier
<a href="http://dx.doi.org/10.1145/3174243.3174250" target="_blank" >10.1145/3174243.3174250</a>

Result language
angličtina
Original language name
Configurable FPGA Packet Parser for Terabit Networks with Guaranteed Wire-Speed Throughput
Original language description
As throughput of computer networks is on a constant rise, there is a need for ever-faster packet parsing modules at all points of the networking infrastructure. Parsing is a crucial operation which has an influence on the final throughput of a network device. Moreover, this operation must precede any kind of further traffic processing like filtering/classification, deep packet inspection, and so on. This paper presents a parser architecture which is capable to currently scale up to a terabit throughput in a single FPGA, while the overall processing speed is sustained even on the shortest frame lengths and for an arbitrary number of supported protocols. The architecture of our parser can be also automatically generated from a high-level description of a protocol stack in the P4 language which makes the rapid deployment of new protocols considerably easier. The results presented in the paper confirm that our automatically generated parsers are capable of reaching an effective throughput of over 1 Tbps (or more than 2000 Mpps) on the Xilinx UltraScale+ FPGAs and around 800 Gbps (or more than 1200 Mpps) on their previous generation Virtex-7 FPGAs.
Czech name
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Czech description
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Project
Result was created during the realization of more than one project. More information in the Projects tab.
Continuities
P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)

Publication year
2018
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Article name in the collection
Proceedings of the 2018 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays
ISBN
978-1-4503-5614-5
ISSN
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e-ISSN
neuvedeno
Number of pages
10
Pages from-to
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Publisher name
ACM
Place of publication
New York, NY, USA
Event location
Monterey, CALIFORNIA, USA
Event date
Feb 25, 2018
Type of event by nationality
WRD - Celosvětová akce
UT code for WoS article
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