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Implementation of (Normalised) RLS Lattice on Virtex.

The result's identifiers

  • Result code in IS VaVaI

    <a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F67985556%3A_____%2F01%3A16010111" target="_blank" >RIV/67985556:_____/01:16010111 - isvavai.cz</a>

  • Result on the web

  • DOI - Digital Object Identifier

Alternative languages

  • Result language

    angličtina

  • Original language name

    Implementation of (Normalised) RLS Lattice on Virtex.

  • Original language description

    The LNS implementation of the LRLS algorithms in a FPGA offers better speed than C30/C40 DSP floating-point and provides low-cost, efficient solution for different system-on-chip applications. The resulting RLS Lattice cores operate with 24-bit precisionfixed-point input/output signals. Therefore, the internal conversion to the log domain and the internal LNS operation can be hidden from the user. This presented work provides significant speedup without any loss of precision.

  • Czech name

  • Czech description

Classification

  • Type

    D - Article in proceedings

  • CEP classification

    JC - Computer hardware and software

  • OECD FORD branch

Result continuities

  • Project

  • Continuities

    Z - Vyzkumny zamer (s odkazem do CEZ)

Others

  • Publication year

    2001

  • Confidentiality

    S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Data specific for result type

  • Article name in the collection

    Field-Programmable Logic and Applications. Proceedings.

  • ISBN

    3-540-42499-7

  • ISSN

  • e-ISSN

  • Number of pages

    10

  • Pages from-to

    91-100

  • Publisher name

    Springer

  • Place of publication

    Berlin

  • Event location

    Belfast [IE]

  • Event date

    Aug 27, 2001

  • Type of event by nationality

    WRD - Celosvětová akce

  • UT code for WoS article