FPGA implementation of logarithmic unit core.

Result code in IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F67985556%3A_____%2F01%3A16010114" target="_blank" >RIV/67985556:_____/01:16010114 - isvavai.cz</a>

Result on the web

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DOI - Digital Object Identifier

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Result language

angličtina

Original language name

FPGA implementation of logarithmic unit core.

Original language description

Implementation of floatig point in FPGA (Field Programmable Gate Arrays) is not easy. Paper presents FPGA core which implements these operations by representation of floating point numbers as 32-bit integer (fixed point) logarithm. Basic arithmetical operations are performed in the logarithm numbering system (LNS) suitable for FPGA. First, we describe Matlab library emulating bit-exactly the properties of the final hardware.

Czech name

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Czech description

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Type

D - Article in proceedings

CEP classification

JC - Computer hardware and software

OECD FORD branch

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Project

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Continuities

Z - Vyzkumny zamer (s odkazem do CEZ)

Publication year

2001

Confidentiality

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Article name in the collection

Embedded Intelligence 2001.

ISBN

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ISSN

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e-ISSN

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Number of pages

8

Pages from-to

547-554

Publisher name

Design & Elektronik

Place of publication

Nürnberg

Event location

Nürnberg [DE]

Event date

Feb 14, 2001

Type of event by nationality

WRD - Celosvětová akce

UT code for WoS article

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