Pipelined implementations of the A Priory Error-Feedback LSL algorithm using logarithmic arithmetic.
The result's identifiers
Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F67985556%3A_____%2F02%3A16020130" target="_blank" >RIV/67985556:_____/02:16020130 - isvavai.cz</a>
Result on the web
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DOI - Digital Object Identifier
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Alternative languages
Result language
angličtina
Original language name
Pipelined implementations of the A Priory Error-Feedback LSL algorithm using logarithmic arithmetic.
Original language description
In this paper we present several implementations of the Modified A Priori Error-Feedback LSL (EF-LSL) algorithm on the Virtex FPGA. Its computational parallelism and pipelinabilty are important advantages. Internally, the computations are based on the logarithmic number system. We compare 32-bit (SINGLE-ALU or DUAL-ALU version) and 20-bit (QUADRI-ALU versions). We show that the LNS implementation can outperform the standard DSP solution based on 32-bit floating-point processors.
Czech name
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Czech description
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Classification
Type
D - Article in proceedings
CEP classification
JC - Computer hardware and software
OECD FORD branch
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Result continuities
Project
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Continuities
Z - Vyzkumny zamer (s odkazem do CEZ)
Others
Publication year
2002
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů
Data specific for result type
Article name in the collection
Proceedings of the IEEE International Conference on Acoustics, Speech and Signal Processing.
ISBN
0-7803-7403-7
ISSN
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e-ISSN
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Number of pages
4
Pages from-to
2681-2684
Publisher name
IEEE
Place of publication
Orlando
Event location
Orlando [US]
Event date
May 13, 2002
Type of event by nationality
WRD - Celosvětová akce
UT code for WoS article
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