Lattice for FPGAs using logarithmic arithmetic.

Result code in IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F67985556%3A_____%2F02%3A16020051" target="_blank" >RIV/67985556:_____/02:16020051 - isvavai.cz</a>

Result on the web

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DOI - Digital Object Identifier

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Result language

angličtina

Original language name

Lattice for FPGAs using logarithmic arithmetic.

Original language description

Presented here are implementations of a complete RLS Lattice cores for Virtex. Their computational parallelism and ease of pipelining lead to easy mapping on FPGA. Internally, the computations are based on 32bit or 20bit logarithmic arithmetic (LNS). Compared are the 32bit LNS-SINGLE-ALU and 20bit LNS-QUAD-ALU versions. On Virtex XCV2000E-6, these use 27%, 54% or 40% of slices respectively and run at 50, 35 and 42 MHz on the Celoxica RC1000 board.

Czech name

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Czech description

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Type

J_x - Unclassified - Peer-reviewed scientific article (Jimp, Jsc and Jost)

CEP classification

JC - Computer hardware and software

OECD FORD branch

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Project

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Continuities

Z - Vyzkumny zamer (s odkazem do CEZ)

Publication year

2002

Confidentiality

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Name of the periodical

Electronic Engineering Design

ISSN

0013-4902

e-ISSN

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Volume of the periodical

74

Issue of the periodical within the volume

906

Country of publishing house

GB - UNITED KINGDOM

Number of pages

4

Pages from-to

53-56

UT code for WoS article

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EID of the result in the Scopus database

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