Lattice adaptive filter implementation for FPGA.
The result's identifiers
Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F67985556%3A_____%2F03%3A16030026" target="_blank" >RIV/67985556:_____/03:16030026 - isvavai.cz</a>
Result on the web
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DOI - Digital Object Identifier
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Alternative languages
Result language
angličtina
Original language name
Lattice adaptive filter implementation for FPGA.
Original language description
Our poster introduces an innovative RLS Lattice filter implementation for FPGAs. The signal processing applications typically require wide numeric range, and that poses a problem when using an FPGA implementation. Our aaproach is based on arithmetic using logarithmic numeric representation (LNS). The test application - adaptive noise canceller - has been optimized for the Xilinx Virtex devices. It consumes roughly 70% of all logic resources of the XCV800 device and all block memory cells.
Czech name
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Czech description
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Classification
Type
D - Article in proceedings
CEP classification
JC - Computer hardware and software
OECD FORD branch
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Result continuities
Project
<a href="/en/project/LN00B096" target="_blank" >LN00B096: Center for Applied Cybernetics</a><br>
Continuities
P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)<br>Z - Vyzkumny zamer (s odkazem do CEZ)
Others
Publication year
2003
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů
Data specific for result type
Article name in the collection
FPGA 2003 ACM/SIGDA Eleventh ACM International Symposium on Field-Programmable Gate Arrays.
ISBN
1-58113-651-X
ISSN
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e-ISSN
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Number of pages
1
Pages from-to
246
Publisher name
ACM
Place of publication
Monterey
Event location
Monterey [US]
Event date
Feb 23, 2003
Type of event by nationality
WRD - Celosvětová akce
UT code for WoS article
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