Dynamic runtime partial reconfiguration in FPGA.
The result's identifiers
Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F67985556%3A_____%2F03%3A16030106" target="_blank" >RIV/67985556:_____/03:16030106 - isvavai.cz</a>
Result on the web
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DOI - Digital Object Identifier
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Alternative languages
Result language
angličtina
Original language name
Dynamic runtime partial reconfiguration in FPGA.
Original language description
Runtime dynamic reconfiguration of FPGA devices has been an issue of the last decade. Although this feature permits more robust and more flexible designes and devices that posseses it are available on the market, it is not directly supported by the current design tools. This paper presents a simple design that uses true dymnamic reconfiguration for Atmel AT94K devices. The design has been implemented using a special feature of the currently available Figaro IDS5.2 tool in an innovative way.
Czech name
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Czech description
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Classification
Type
D - Article in proceedings
CEP classification
JC - Computer hardware and software
OECD FORD branch
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Result continuities
Project
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Continuities
Z - Vyzkumny zamer (s odkazem do CEZ)
Others
Publication year
2003
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů
Data specific for result type
Article name in the collection
ECMS 2003. 6th International Workshop on Electronics, Control, Measurement and Signals.
ISBN
80-7083-708-X
ISSN
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e-ISSN
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Number of pages
5
Pages from-to
294-298
Publisher name
Technical University
Place of publication
Liberec
Event location
Liberec [CZ]
Event date
Jun 2, 2003
Type of event by nationality
EUR - Evropská akce
UT code for WoS article
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