Design Flow for Reconfigurable MicroBlaze Accelerators

Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F67985556%3A_____%2F08%3A00309834" target="_blank" >RIV/67985556:_____/08:00309834 - isvavai.cz</a>
Result on the web
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DOI - Digital Object Identifier
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Result language
angličtina
Original language name
Design Flow for Reconfigurable MicroBlaze Accelerators
Original language description
We present design flow and related tool-chain supporting modeling, HW-SW co-simulation as well as generation of HDL code for reconfigurable MicroBlaze accelerators. Each accelerator is composed from reprogrammable PicoBlaze sequencing HW supported floating point processing batches executed on local data. The Xilinx MicroBlaze soft-core processor serves as the central CPU with access to the global off chip memory and peripherals. Each coprocessor can be re-programmed during runtime. This provides a framework for a partial dynamic change of the functionality of HW floating point accelerators suitable for FPGA as well as for the custom designs.
Czech name
Návrh rekonfigurovatelných akcelerátorů pro procesor MicroBlaze
Czech description
Článek presentuje metodologii návrhu rekonfigurovatelných akcelerátorů pro FPGA procesor MicroBlaze. Každý akcelerátor může být modifikován za chodu pomocí mikroprogramu.

Project
<a href="/en/project/1M0567" target="_blank" >1M0567: Centre for Applied Cybernetics</a><br>
Continuities
Z - Vyzkumny zamer (s odkazem do CEZ)

Publication year
2008
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Article name in the collection
4th International Workshop on Reconfigurable Communication Centric System-on-Chips Workshop Proceedings
ISBN
978-84-691-3603-4
ISSN
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e-ISSN
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Number of pages
8
Pages from-to
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Publisher name
UPC
Place of publication
Barcelona
Event location
Barcelona
Event date
Jul 9, 2008
Type of event by nationality
EUR - Evropská akce
UT code for WoS article
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