Instruction Set Extensions for Multi-Threading in LEON3
The result's identifiers
Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F67985556%3A_____%2F10%3A00342262" target="_blank" >RIV/67985556:_____/10:00342262 - isvavai.cz</a>
Result on the web
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DOI - Digital Object Identifier
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Alternative languages
Result language
angličtina
Original language name
Instruction Set Extensions for Multi-Threading in LEON3
Original language description
This paper describes instruction set extensions for a variant of multi-threading called micro-threading for the LEON3 SPARCv8 processor. We show an architecture of the developed processor and its key blocks - cache controller, register file, thread scheduler. The processor has been implemented in a Xilinx Virtex2Pro FPGA. The extensions are evaluated in terms of extra resources needed, and the overall performance of the developed processor is evaluated on a simple DSP computation typical for embedded systems.
Czech name
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Czech description
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Classification
Type
D - Article in proceedings
CEP classification
JC - Computer hardware and software
OECD FORD branch
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Result continuities
Project
<a href="/en/project/7E08013" target="_blank" >7E08013: Architecture Paradigms and Programming Languages for Efficient programming of multiple COREs</a><br>
Continuities
Z - Vyzkumny zamer (s odkazem do CEZ)
Others
Publication year
2010
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů
Data specific for result type
Article name in the collection
Proceedings of the13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems
ISBN
978-1-4244-6610-8
ISSN
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e-ISSN
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Number of pages
6
Pages from-to
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Publisher name
IEEE
Place of publication
Los Alamitos
Event location
Vídeň
Event date
Apr 14, 2010
Type of event by nationality
WRD - Celosvětová akce
UT code for WoS article
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