Hardware Support for Fine-Grain Multi-Threading in LEON3

Result code in IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F67985556%3A_____%2F11%3A00380861" target="_blank" >RIV/67985556:_____/11:00380861 - isvavai.cz</a>

Result on the web

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DOI - Digital Object Identifier

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Result language

angličtina

Original language name

Hardware Support for Fine-Grain Multi-Threading in LEON3

Original language description

The article describes instruction set extensions for a variant of multi-threading called micro-threading for the LEON3 SPARCv8 processor. An architecture of the developed processor is presented and its key blocks described - cache controller, register file, thread scheduler. The processor has been implemented in a Xilinx Virtex2Pro and Virtex5 FPGAs. The extensions are evaluated in terms of extra resources needed, and the overall performance of the developed processor is shown for a simple DSP computation typical for embedded systems.

Czech name

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Czech description

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Type

J_x - Unclassified - Peer-reviewed scientific article (Jimp, Jsc and Jost)

CEP classification

JC - Computer hardware and software

OECD FORD branch

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Project

<a href="/en/project/7E08013" target="_blank" >7E08013: Architecture Paradigms and Programming Languages for Efficient programming of multiple COREs</a><br>

Continuities

P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)

Publication year

2011

Confidentiality

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Name of the periodical

Carpathian Journal of Electronic and Computer Engineering

ISSN

1844-9689

e-ISSN

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Volume of the periodical

4

Issue of the periodical within the volume

1

Country of publishing house

RO - ROMANIA

Number of pages

8

Pages from-to

27-34

UT code for WoS article

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EID of the result in the Scopus database

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