A Survey of Hardware Technologies for Mixed-Critical Integration Explored in the Project EMC2
The result's identifiers
Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F67985556%3A_____%2F17%3A00479509" target="_blank" >RIV/67985556:_____/17:00479509 - isvavai.cz</a>
Result on the web
<a href="http://dx.doi.org/10.1007/978-3-319-66284-8" target="_blank" >http://dx.doi.org/10.1007/978-3-319-66284-8</a>
DOI - Digital Object Identifier
<a href="http://dx.doi.org/10.1007/978-3-319-66284-8" target="_blank" >10.1007/978-3-319-66284-8</a>
Alternative languages
Result language
angličtina
Original language name
A Survey of Hardware Technologies for Mixed-Critical Integration Explored in the Project EMC2
Original language description
Technologies described in the paper provide hardware solution from architectural level up to the peripheral and application specific hardware. Moreover paper presents extendable multiprocessing hardware platform based on Zynq hybrid SoC, an asymmetric multiprocessing in video processing architecture, Time-of-Flight sensor and image processing architecture, predictable and verifiable Network-on-Chip (NoC), heterogeneous time-triggered NoC architecture, virtual hardware platform, software-driven energy consumption optimization techniques, and time-predictable L1 cache memory. The application of hybrid SoC platforms opposed to COTS multi-core architecture provides multiple benefits and can be seen as a viable bridging solution in the gap between single- and multi-core architectures.
Czech name
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Czech description
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Classification
Type
D - Article in proceedings
CEP classification
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OECD FORD branch
20206 - Computer hardware and architecture
Result continuities
Project
<a href="/en/project/7H14005" target="_blank" >7H14005: EMC2 - Embedded Multi-Core Systems for Mixed Criticality Applications in Dynamic and Changeable Real-Time Environments</a><br>
Continuities
P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)
Others
Publication year
2017
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů
Data specific for result type
Article name in the collection
Computer Safety, Reliability, and Security : SAFECOMP 2017 Workshops, ASSURE, DECSoS, SASSUR, TELERISE, and TIPS
ISBN
978-3-319-66283-1
ISSN
0302-9743
e-ISSN
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Number of pages
13
Pages from-to
127-140
Publisher name
Springer
Place of publication
Cham
Event location
Trento
Event date
Sep 12, 2017
Type of event by nationality
EUR - Evropská akce
UT code for WoS article
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