The polynomial and linear time hierarchies in V-0

Result code in IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F67985840%3A_____%2F09%3A00337059" target="_blank" >RIV/67985840:_____/09:00337059 - isvavai.cz</a>

Result on the web

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DOI - Digital Object Identifier

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Result language

angličtina

Original language name

The polynomial and linear time hierarchies in V-0

Original language description

We show that the bounded arithmetic theory V-0 does not prove that the polynomial time hierarchy collapses to the linear time hierarchy (without parameters). The result follows from a lower bound for bounded depth circuits computing prefix parity, wherethe circuits are allowed some auxiliary input; we derive this from a theorem of Ajtai.

Czech name

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Czech description

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Type

J_x - Unclassified - Peer-reviewed scientific article (Jimp, Jsc and Jost)

CEP classification

BA - General mathematics

OECD FORD branch

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Project

<a href="/en/project/LC505" target="_blank" >LC505: Eduard Čech Center for Algebra and Geometry</a><br>

Continuities

Z - Vyzkumny zamer (s odkazem do CEZ)

Publication year

2009

Confidentiality

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Name of the periodical

Mathematical Logic Quarterly

ISSN

0942-5616

e-ISSN

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Volume of the periodical

55

Issue of the periodical within the volume

5

Country of publishing house

DE - GERMANY

Number of pages

6

Pages from-to

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UT code for WoS article

000270961200004

EID of the result in the Scopus database

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