Phase locked loops (PPL) design.

Result code in IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F67985882%3A_____%2F00%3A13000059" target="_blank" >RIV/67985882:_____/00:13000059 - isvavai.cz</a>

Result on the web

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DOI - Digital Object Identifier

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Result language

angličtina

Original language name

Phase locked loops (PPL) design.

Original language description

The sampled and higher order systems are discussed and means for stability checking, with the computer simulation of the Bode plots, are mentioned. It is shown that computer plotting of the PLL transfer function H(s) and 1-H(s), with the assistance of the open loop gain G(s), provides many information influence about noise of different noise sources; i.e., noise of the reference oscillator, of the voltage controlled oscillator, of the phase detector and of inevitable filters.

Czech name

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Czech description

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Type

D - Article in proceedings

CEP classification

JA - Electronics and optoelectronics

OECD FORD branch

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Project

<a href="/en/project/GA102%2F00%2F0958" target="_blank" >GA102/00/0958: Investigation of frequency stability of local generators</a><br>

Continuities

P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)

Publication year

2000

Confidentiality

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Article name in the collection

Aplikovaná elektronika'2000. Sborník referátů mezinárodní konference.

ISBN

80-7082-650-9

ISSN

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e-ISSN

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Number of pages

4

Pages from-to

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Publisher name

Vydavatelství Západočeské univerzity

Place of publication

Plzeň

Event location

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Event date

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Type of event by nationality

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UT code for WoS article

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