IP Function of CAN Frames Generator and Error Injector for CAN Tester Card

Result code in IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F68407700%3A21220%2F03%3A03088465" target="_blank" >RIV/68407700:21220/03:03088465 - isvavai.cz</a>

Result on the web

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DOI - Digital Object Identifier

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Result language

angličtina

Original language name

IP Function of CAN Frames Generator and Error Injector for CAN Tester Card

Original language description

This paper describes the design of an FPGA IP function for CAN frames generator with the ability of generating frames with errors including errors in bit timing. Generator is designed to cooperate with CAN Analyzer IP function placed on PCI card in the same field programmable gate array (FPGA). Behavior of the generator is programmable by means of "control sequence", so it (in conjunction with CAN Analyzer) can also emulate behavior of any CAN bus device.

Czech name

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Czech description

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Type

D - Article in proceedings

CEP classification

JA - Electronics and optoelectronics

OECD FORD branch

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Project

<a href="/en/project/LN00B073" target="_blank" >LN00B073: Josef Božek Research Center of Engine and Automotive Engineering</a><br>

Continuities

P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)

Publication year

2003

Confidentiality

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Article name in the collection

Applied Electronics

ISBN

80-7082-951-6

ISSN

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e-ISSN

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Number of pages

4

Pages from-to

59-62

Publisher name

ZČU Plzeň

Place of publication

Plzeň

Event location

Plzeň

Event date

Sep 10, 2003

Type of event by nationality

EUR - Evropská akce

UT code for WoS article

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