Minimization of the Hamming Code Generator in Self Checking Circuits

Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F68407700%3A21230%2F04%3A03099879" target="_blank" >RIV/68407700:21230/04:03099879 - isvavai.cz</a>
Result on the web
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DOI - Digital Object Identifier
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Result language
angličtina
Original language name
Minimization of the Hamming Code Generator in Self Checking Circuits
Original language description
The paper focuses on the minimization of the area overhead of check bits generator in the online BIST for circuits implemented in FPGAs. We have used error detection codes (ED codes) to ensure the self-checking property. The newly proposed simplificationmethod consists of converting the duplicate circuit into a two-level network, for which the check-bits are generated. Then the outputs of the circuit are reduced to these check-bits only; the original outputs can be omitted. After that, a multi-level network is synthesized for this circuit. This notion enables us to significantly reduce the resulting logic.
Czech name
Není k dispozici
Czech description
Není k dispozici

Project
<a href="/en/project/GA102%2F04%2F2137" target="_blank" >GA102/04/2137: Design of highly reliable control systems built on dynamically reconfigurable FPGAs.</a><br>
Continuities
Z - Vyzkumny zamer (s odkazem do CEZ)

Publication year
2004
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Article name in the collection
Proceedings of the International Workshop on Discrete-Event System Design - DESDes'04
ISBN
83-89712-15-6
ISSN
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e-ISSN
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Number of pages
6
Pages from-to
161-166
Publisher name
University of Zielona Gora
Place of publication
Zielona Gora
Event location
Dychow
Event date
Sep 15, 2004
Type of event by nationality
WRD - Celosvětová akce
UT code for WoS article
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