An Efficient Multiple-Parity Generator Design for On-Line Testing on FPGA

Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F68407700%3A21230%2F08%3A00145451" target="_blank" >RIV/68407700:21230/08:00145451 - isvavai.cz</a>
Result on the web
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DOI - Digital Object Identifier
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Result language
angličtina
Original language name
An Efficient Multiple-Parity Generator Design for On-Line Testing on FPGA
Original language description
We propose a method to efficiently design a "parity generator", which is a stand-alone block producing multiple parity bits of a given circuit. The parity generator is designed by duplicating the original circuit, XOR-ing given groups of its outputs andresynthesizing the whole circuit. The resulting circuitry is mostly smaller than the original circuit. The major task to be solved is to properly select the groups of outputs to be XORed to obtain multiple parity bits and maximally reduce the generator size. A method based on principles of the FC-Min minimizer is proposed in this paper. The parity generator is exploited in on line diagnostics, to design self-checking circuits based on a modified duplex system.
Czech name
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Czech description
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Project
<a href="/en/project/FI-IM4%2F149" target="_blank" >FI-IM4/149: *Research and Development of High-rate Microwave Line Featured by QAM Modulation and the Transmission Speed of 155 Mbit/s.</a><br>
Continuities
Z - Vyzkumny zamer (s odkazem do CEZ)

Publication year
2008
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Article name in the collection
Proceedings of 11th Euromicro Conference on Digital System Design
ISBN
978-0-7695-3277-6
ISSN
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e-ISSN
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Number of pages
4
Pages from-to
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Publisher name
IEEE Computer Society
Place of publication
Los Alamitos
Event location
Parma
Event date
Sep 3, 2008
Type of event by nationality
WRD - Celosvětová akce
UT code for WoS article
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