Fault Tolerant System Design Method Based on Self-Checking Circuits

Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F68407700%3A21230%2F06%3A03120136" target="_blank" >RIV/68407700:21230/06:03120136 - isvavai.cz</a>
Result on the web
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DOI - Digital Object Identifier
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Result language
angličtina
Original language name
Fault Tolerant System Design Method Based on Self-Checking Circuits
Original language description
This paper describes a highly reliable digital circuit design method based on totally self checking blocks implemented in FPGAs. The bases of the self checking blocks are parity predictors. The parity predictor design method based on multiple parity groups is proposed. Proper parity groups are chosen in order to obtain minimal area overhead and to decrease the number of undetectable faults.
Czech name
Fault Tolerant System Design Method Based on Self-Checking Circuits
Czech description
This paper describes a highly reliable digital circuit design method based on totally self checking blocks implemented in FPGAs. The bases of the self checking blocks are parity predictors. The parity predictor design method based on multiple parity groups is proposed. Proper parity groups are chosen in order to obtain minimal area overhead and to decrease the number of undetectable faults.

Project
<a href="/en/project/GA102%2F04%2F0737" target="_blank" >GA102/04/0737: Modern methods of digital system synthesis</a><br>
Continuities
Z - Vyzkumny zamer (s odkazem do CEZ)

Publication year
2006
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Article name in the collection
Proceedings IOLTS 2006 12th IEEE International On-Line Testing Symposium
ISBN
0-7695-2620-9
ISSN
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e-ISSN
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Number of pages
2
Pages from-to
185-186
Publisher name
IEEE Computer Society
Place of publication
Los Alamitos
Event location
Como
Event date
Jul 10, 2006
Type of event by nationality
WRD - Celosvětová akce
UT code for WoS article
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