Dependability Computation for Fault Tolerant Reconfigurable Duplex System

Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F68407700%3A21230%2F06%3A03120122" target="_blank" >RIV/68407700:21230/06:03120122 - isvavai.cz</a>
Result on the web
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DOI - Digital Object Identifier
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Result language
angličtina
Original language name
Dependability Computation for Fault Tolerant Reconfigurable Duplex System
Original language description
This paper describes a design method for highly reliable digital circuits based on totally self checking blocks implemented in FPGAs. The dependability model and dependability calculations are proposed. The self checking blocks are based on a parity predictor. These blocks are linked together to form a compound design. Our adapted duplex system is used as a basic structure to increase availability parameters and protect system against Single Even Upsets (SEUs). This adapted duplex system is realized bytwo FPGAs, where each FPGA can be reconfigured when a fault is detected. Availability parameters have been calculated by dependability Markov models.
Czech name
Není k dispozici
Czech description
Není k dispozici

Project
<a href="/en/project/GA102%2F04%2F2137" target="_blank" >GA102/04/2137: Design of highly reliable control systems built on dynamically reconfigurable FPGAs.</a><br>
Continuities
Z - Vyzkumny zamer (s odkazem do CEZ)

Publication year
2006
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Article name in the collection
Proceedings of the 2006 IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems
ISBN
1-4244-0184-4
ISSN
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e-ISSN
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Number of pages
3
Pages from-to
100-102
Publisher name
CTU Publishing House
Place of publication
Praha
Event location
Praha
Event date
Apr 18, 2006
Type of event by nationality
EUR - Evropská akce
UT code for WoS article
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