Highly Reliable Design Based on TSC Circuits

Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F68407700%3A21230%2F05%3A03109967" target="_blank" >RIV/68407700:21230/05:03109967 - isvavai.cz</a>
Result on the web
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DOI - Digital Object Identifier
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Result language
angličtina
Original language name
Highly Reliable Design Based on TSC Circuits
Original language description
This paper deals with architecture of highly reliable digital circuits based on totally self checking blocks implemented in FPGAs. A duplex system is used as a basic structure of this reliable design. The whole design implemented in FPGA is divided intoindividual functional parts. Every part is modified to ensure totally self checking properties, which are calculated using our method of detailed fault classification. The reconfiguration process is utilized to increase reliability parameters. Combinational circuit benchmarks have been considered in this work to compute the quality of the adapted duplex system. The benchmarks are represented by two level networks (truth table). All of our experimental results are obtained by XILINX FPGA implementation by EDA tools.
Czech name
Vysoce spolehlivý návrh TSC obvodů
Czech description
Článek se zabýva návrhem vysoce spolehlivých obvod implementovaných pomocí FPGA obvodů. Návrh je založen na jednoduchém zdvojení obvodů splňujících podminky pro návrh TSC obvodu.

Project
<a href="/en/project/GA102%2F03%2F0672" target="_blank" >GA102/03/0672: Research of methods and tools for verification of embedded computer system fault tolerance</a><br>
Continuities
Z - Vyzkumny zamer (s odkazem do CEZ)

Publication year
2005
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

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