Performance Tuning of Iterative Algorithms in Signal Processing

Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F68407700%3A21230%2F05%3A03109440" target="_blank" >RIV/68407700:21230/05:03109440 - isvavai.cz</a>
Result on the web
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DOI - Digital Object Identifier
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Result language
angličtina
Original language name
Performance Tuning of Iterative Algorithms in Signal Processing
Original language description
Presented high-level synthesis describes scheduling for wide class of DSP algorithms. Several FPGA vendors or even ASIC designs are targeted via Handel-C compiled by Celoxica DK3.1 compiler. Using our approach, the designer can easily change type of usedpipelined arithmetic modules and then check new performance. The optimal time schedule is found by cyclic scheduling using Integer Linear Programming while minimizing the schedule period in the terms of clock cycles. Experimental results in HW implementation, performed on logarithmic arithmetic and floating-point arithmetic, confirm significant influence of the period on the resulting performance of DSP algorithms.
Czech name
Není k dispozici
Czech description
Není k dispozici

Project
<a href="/en/project/1M0567" target="_blank" >1M0567: Centre for Applied Cybernetics</a><br>
Continuities
P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)

Publication year
2005
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Article name in the collection
International Conference on Field Programmable Logic and Applications (FPL)
ISBN
0-7803-9362-7
ISSN
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e-ISSN
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Number of pages
9
Pages from-to
404-412
Publisher name
IEEE
Place of publication
Toronto
Event location
Tampere
Event date
Aug 24, 2005
Type of event by nationality
WRD - Celosvětová akce
UT code for WoS article
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