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Off-line Scheduling for FPGAs

The result's identifiers

  • Result code in IS VaVaI

    <a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F68407700%3A21230%2F08%3A00145656" target="_blank" >RIV/68407700:21230/08:00145656 - isvavai.cz</a>

  • Alternative codes found

    RIV/68407700:21230/07:00134000

  • Result on the web

  • DOI - Digital Object Identifier

Alternative languages

  • Result language

    angličtina

  • Original language name

    Off-line Scheduling for FPGAs

  • Original language description

    The objective of this course is to provide an overview of different off-line scheduling problems found in embedded systems. Our lecture is motivated by digital signal processing (DSP) applications on FPGAs (Field-Programmable Gate Array) - hardware architectures hosting several arithmetic units. We will show how scheduling with generalized precedence constraints can be used to model typical scheduling problems on FPGAs and how cyclic scheduling can be used to optimize computation performance of DSP applications.

  • Czech name

  • Czech description

Classification

  • Type

    O - Miscellaneous

  • CEP classification

    JC - Computer hardware and software

  • OECD FORD branch

Result continuities

  • Project

    Result was created during the realization of more than one project. More information in the Projects tab.

  • Continuities

    P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)

Others

  • Publication year

    2007

  • Confidentiality

    S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů