Dynamic Reconfiguration in FPGA-Based SoC Designs
The result's identifiers
Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F68407700%3A21230%2F05%3A03110049" target="_blank" >RIV/68407700:21230/05:03110049 - isvavai.cz</a>
Result on the web
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DOI - Digital Object Identifier
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Alternative languages
Result language
angličtina
Original language name
Dynamic Reconfiguration in FPGA-Based SoC Designs
Original language description
This paper discusses architectural issues arising from the use of dynamic reconfiguration and shows a possible use of dynamic reconfiguration to extend and accelerate a computation performed in system-on-a-chip designs with microprocessors with fixed instruction sets.
Czech name
Není k dispozici
Czech description
Není k dispozici
Classification
Type
D - Article in proceedings
CEP classification
JC - Computer hardware and software
OECD FORD branch
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Result continuities
Project
<a href="/en/project/1M0567" target="_blank" >1M0567: Centre for Applied Cybernetics</a><br>
Continuities
P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)
Others
Publication year
2005
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů
Data specific for result type
Article name in the collection
Advanced Computer Architecture and Compilation for Embeded Systems
ISBN
90 382 0802 2
ISSN
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e-ISSN
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Number of pages
4
Pages from-to
35-38
Publisher name
Network of Excellence HiPEAC
Place of publication
Ghent
Event location
L'Aquila
Event date
Jul 23, 2005
Type of event by nationality
WRD - Celosvětová akce
UT code for WoS article
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