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Dynamic Programmable Logic Reconfiguration for Zynq

The result's identifiers

  • Result code in IS VaVaI

    <a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F67985556%3A_____%2F15%3A00443453" target="_blank" >RIV/67985556:_____/15:00443453 - isvavai.cz</a>

  • Result on the web

  • DOI - Digital Object Identifier

Alternative languages

  • Result language

    angličtina

  • Original language name

    Dynamic Programmable Logic Reconfiguration for Zynq

  • Original language description

    The architecture of the Zynq all programmable SoC from Xilinx consists of Dual ARM Cortex-A9 cores with NEON DSP/FPU engine and of programmable logic (PL). This demo shows how the PL can be fully reconfigured without using partial dynamic reconfiguration. This way, at the cost of the longer time needed for reconfiguration of PL we can cover 90% typical applications using dynamic reconfiguration where CPU cores are running while PL adapts. The dynamic reconfiguration demo consists from two bitstreams forPL configuration and one pre-compiled software code. The software application demonstrates the PL reconfiguration. It also allows to control reset and clocks for PL. The precompiled demo prepared for ZC702 SD card can be found in boot_image/sd_card.

  • Czech name

  • Czech description

Classification

  • Type

    G<sub>funk</sub> - Functional sample

  • CEP classification

    IN - Informatics

  • OECD FORD branch

Result continuities

  • Project

    <a href="/en/project/7H14005" target="_blank" >7H14005: EMC2 - Embedded Multi-Core Systems for Mixed Criticality Applications in Dynamic and Changeable Real-Time Environments</a><br>

  • Continuities

    P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)

Others

  • Publication year

    2015

  • Confidentiality

    S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Data specific for result type

  • Internal product ID

    plreconf

  • Numerical identification

  • Technical parameters

    libovolny počet bitstreamů ze SD karty

  • Economical parameters

    zvýšení funkční hustoty v FPGA obvodu

  • Application category by cost

  • Owner IČO

    67985556

  • Owner name

    ÚTIA AV ČR, v.v

  • Owner country

    CZ - CZECH REPUBLIC

  • Usage type

    A - K využití výsledku jiným subjektem je vždy nutné nabytí licence

  • Licence fee requirement

    Z - Poskytovatel licence na výsledek nepožaduje v některých případech licenční poplatek

  • Web page