Framework for Fast Prototyping of Applications running on Reconfigurable Systems on Chip

Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26230%2F13%3APU106392" target="_blank" >RIV/00216305:26230/13:PU106392 - isvavai.cz</a>
Result on the web
<a href="http://www.fit.vutbr.cz/research/pubs/all.php?id=10393" target="_blank" >http://www.fit.vutbr.cz/research/pubs/all.php?id=10393</a>
DOI - Digital Object Identifier
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Result language
angličtina
Original language name
Framework for Fast Prototyping of Applications running on Reconfigurable Systems on Chip
Original language description
Recently introduced chips with ARM based processors and programmable logic provide huge potential for digital signal processing, networking and other applications. Many IP cores and operating systems have been prepared for these chips to simplify the development process. Nevertheless, the integration of IP cores and operating system is not covered by any development tool yet. Developers have to design, implement and debug the communication between hardware and software part of the application. Therefore we propose Reconfigurable System on Chip (RSoC) Framework to support rapid prototyping of applications running on FPGA chips with a processor. The framework consists of FPGA logic and OS drivers to support communication between application core in the FPGA and application software on the host processor. Moreover, the framework allows to configure automatically address space of components in the FPGA and supports dynamic loading of drivers according to the FPGA configuration. The developer can focus only on the application software and accelerating core. For demonstration purposes, the framework is exploited in the example of a video processing application, where an image filter is running in the software and than is accelerated in the FPGA.
Czech name
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Czech description
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Project
<a href="/en/project/VG20102015022" target="_blank" >VG20102015022: Modern tools for detection and mitigation of cyber criminality on the New Generation Internet</a><br>
Continuities
P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)

Publication year
2013
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Article name in the collection
Proceedings of the 2013 Conference on Design & Architectures for Signal & Image Processing
ISBN
979-10-92279-01-6
ISSN
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e-ISSN
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Number of pages
2
Pages from-to
355-356
Publisher name
European Electronic Chips & Systems design Initiative
Place of publication
Cagliari
Event location
Cagliari
Event date
Oct 8, 2013
Type of event by nationality
WRD - Celosvětová akce
UT code for WoS article
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