Concept of Edge-Controlled Many-Valued R-S Memory Circuit
The result's identifiers
Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F68407700%3A21230%2F06%3A00125933" target="_blank" >RIV/68407700:21230/06:00125933 - isvavai.cz</a>
Result on the web
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DOI - Digital Object Identifier
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Alternative languages
Result language
angličtina
Original language name
Concept of Edge-Controlled Many-Valued R-S Memory Circuit
Original language description
In a previous paper we have presented our approach to many-valued memory circuits based on a generalization of the R-S memory circuit (also known as R-S flip-flop) known in the two-valued logic. We have also shown a construction of a level-controlled many-valued memory circuit. In this paper we use this knowledge to construct an edge-controlled many-valued memory circuit of type ``master-slave''. We discuss several implementational problems related to the fact that the circuit is many-valued.
Czech name
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Czech description
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Classification
Type
D - Article in proceedings
CEP classification
JD - Use of computers, robotics and its application
OECD FORD branch
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Result continuities
Project
<a href="/en/project/1ET101210407" target="_blank" >1ET101210407: Multi-camera system for modeling and recognition of events</a><br>
Continuities
P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)
Others
Publication year
2006
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů
Data specific for result type
Article name in the collection
2006 IEEE Congress on Evolutionary Computation
ISBN
0-7803-9489-5
ISSN
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e-ISSN
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Number of pages
5
Pages from-to
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Publisher name
IEEE Computer Society
Place of publication
Los Alamitos
Event location
Vancouver
Event date
Jul 16, 2006
Type of event by nationality
WRD - Celosvětová akce
UT code for WoS article
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