An Accelerator for Kohonen Self-Organizing Maps

Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F68407700%3A21230%2F06%3A00126094" target="_blank" >RIV/68407700:21230/06:00126094 - isvavai.cz</a>
Result on the web
—
DOI - Digital Object Identifier
—

Result language
angličtina
Original language name
An Accelerator for Kohonen Self-Organizing Maps
Original language description
In this work we are describing hardware implementation of Kohonen Self-Organizing Map. The essential feature of that kind of artificial neural networks is that they have ability to visualize data, i.e. transform data from n-dimensional data vectors intotwo dimensional map. We use this feature for facilitating neurologist diagnosis and prognosis. Having used the KSOM for speech signal processing, we came up against the challenging complexity and time-consuming characters of training and classification.Our motivation was to find a modification suitable for hardware implementation of Kohonen maps. We examined existing neurocomputers and decided to work out our own neurocomputer with a different, more suitable architecture. Our neurocomputer is being realized on FPGA. VHDL has been selected for the hardware description. Presented neurocomputer can be easily modified and simulated on personal computer with free available development tools for VHDL.
Czech name
—
Czech description
—

Publication year
2006
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Article name in the collection
Digital Technologies 2006 - 3rd International Workshop
ISBN
80-8070-637-9
ISSN
—
e-ISSN
—
Number of pages
6
Pages from-to
—
Publisher name
Žilinská universita, Elektrotechnická fakulta
Place of publication
Žilina
Event location
Žilina
Event date
Dec 1, 2006
Type of event by nationality
WRD - Celosvětová akce
UT code for WoS article
—

Similar results(10)