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New Criteria Enhancing Robustness and Efficiency of Solving Systems of Circuit Equations

The result's identifiers

  • Result code in IS VaVaI

    <a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F68407700%3A21230%2F06%3A03121535" target="_blank" >RIV/68407700:21230/06:03121535 - isvavai.cz</a>

  • Result on the web

  • DOI - Digital Object Identifier

Alternative languages

  • Result language

    angličtina

  • Original language name

    New Criteria Enhancing Robustness and Efficiency of Solving Systems of Circuit Equations

  • Original language description

    A new robust algorithm suppressing possible divergence of the Newton-Raphson method for solving the nonlinear circuit equations is proposed in both static and dynamic domains. For enhancing the efficiency of repeated solutions of linear systems necessaryin the Newton-Raphson method, a new modification of the Markowitz criterion is suggested which is compatible with the fast modes of the LU factorization. The modified criterion consists in an estimation of probabilities of the fill-in enlargement. The probabilities are determined for all columns of the system matrix before the LU factorization, where the column probability is calculated as the average value of the probabilities for all the column elements. Finally, the columns are reordered so that first and last should be those with the minimum and maximum probabilities, respectively. As a verification of the proposed algorithm, a comprehensive set of numerical tests is described for circuits chosen from various parts of electronics.

  • Czech name

    Nová kritéria pro zvýšení robustnosti a účinnosti řešení soustav obvodových rovnic

  • Czech description

    Nová kritéria pro zvýšení robustnosti a účinnosti řešení soustav obvodových rovnic.

Classification

  • Type

    D - Article in proceedings

  • CEP classification

    JA - Electronics and optoelectronics

  • OECD FORD branch

Result continuities

  • Project

    <a href="/en/project/GA102%2F05%2F0277" target="_blank" >GA102/05/0277: Current- and hybrid-mode circuits for analog signal processing</a><br>

  • Continuities

    Z - Vyzkumny zamer (s odkazem do CEZ)

Others

  • Publication year

    2006

  • Confidentiality

    S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Data specific for result type

  • Article name in the collection

    Proceedings of the 2006 IEEE Asia Pacific Conference on Circuits and Systems

  • ISBN

    978-1-4244-0386-8

  • ISSN

  • e-ISSN

  • Number of pages

    5

  • Pages from-to

    1-5

  • Publisher name

    IEEE

  • Place of publication

    Piscataway

  • Event location

    Singapore

  • Event date

    Dec 4, 2006

  • Type of event by nationality

    WRD - Celosvětová akce

  • UT code for WoS article