FPGA Based Testing of Hybrid Real-time Systems

Result code in IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F68407700%3A21230%2F07%3A00128621" target="_blank" >RIV/68407700:21230/07:00128621 - isvavai.cz</a>

Result on the web

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DOI - Digital Object Identifier

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Result language

angličtina

Original language name

FPGA Based Testing of Hybrid Real-time Systems

Original language description

This presentation presents a design methodology for a hybrid Hardware-in-the-Loop (HIL) tester tool, based on both the discrete event system theory, given by timed automata, and the continuous systems theory, given by difference equations.It is implemented using an FPGA platform that proposes speed enhancement, time accuracy and extensibility as well. We focuse on automatic generation of discrete event system specificaly timed automata into FPGA and we link them with continuous systems generated as filters in fixed point arithmetics.The paper shows a methodology which employs widely used tools (Matlab used for controller design and simulation and UPPAAL for discrete event system design and model checking) as a user interface, and which generates the FPGA based tester tool.

Czech name

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Czech description

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Type

O - Miscellaneous

CEP classification

JC - Computer hardware and software

OECD FORD branch

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Project

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Continuities

Z - Vyzkumny zamer (s odkazem do CEZ)

Publication year

2007

Confidentiality

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů